发明名称 Buffering missed requests in processor caches
摘要 The present disclosure relates to caches that are capable of improving processor performance. In some embodiments, among others, a cache request is received, and logic within the cache determines whether the received cache request results in a hit on the cache. If the cache request results in a hit on the cache, then that cache request is serviced. Conversely, if the cache request does not result in a hit (e.g., miss, miss-on-miss, hit-on-miss, etc.), then information related to the received cache request is stored in a missed request table. For some embodiments, missed read requests are stored in a missed read request table, while missed write requests are stored in a missed write request table.
申请公布号 US2007067572(A1) 申请公布日期 2007.03.22
申请号 US20050229939 申请日期 2005.09.19
申请人 VIA TECHNOLOGIES, INC. 发明人 JIAO YANG;CHEN YIPING;CHEN WEN-CHUNG
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
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