发明名称 METHOD OF INCREASING ALIGNMENT TOLERANCES FOR INTERCONNECT STRUCTURES
摘要 <P>PROBLEM TO BE SOLVED: To increase alignment tolerances between conductive projections and electric parts formed on a semiconductor wafer. <P>SOLUTION: In one implementation, the conductive projection including an upper surface and a side surface joined therewith to define a corner region, is formed over a substrate surface area. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug having an uppermost surface is formed over a substrate node location between a pair of conductive lines. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, the conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and the conductive plug material containing greater concentrations of dopant is etched at a greater rate than that of plug material containing lower concentrations of dopant. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007073979(A) 申请公布日期 2007.03.22
申请号 JP20060285899 申请日期 2006.10.20
申请人 MICRON TECHNOLOGY INC 发明人 FISCHER MARK;ZAHURAK JOHN K;GRAETTINGER THOMAS M;PAREKH KUNAL
分类号 H01L21/302;H01L21/768;G03F7/075;G03F7/16;H01L21/3065;H01L21/8242;H01L23/522;H01L27/108 主分类号 H01L21/302
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