| 摘要 |
PROBLEM TO BE SOLVED: To provide a frequency multiplier apparatus at a low cost with high precision capable of maintaining the precision of an output signal. SOLUTION: The frequency multiplier apparatus uses two count permission signals UCE1, UCE2, being objects of correction, output every other period of a reference signal PREF and in a logically inverted relation and activates two counter data latch circuits 4a, 4b of the same configuration separately at periods deviated by one period of the reference signal PREF. Then the frequency multiplier apparatus repeats the correction of frequency control data CD1 to CD12(c) by each period of the reference signal PREF to produce an output signal POUT resulting from multiplying the frequency of the reference signal PREF by a multiple of total number of polyphase clocks R1 to R16. A count of an output clock RCK (=R13) is reflected on the frequency control data CD1 to CD12(c) and a correction delay time being a time required until the new frequency control data are produced is a time for one period of the reference signal PREF. COPYRIGHT: (C)2007,JPO&INPIT
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