发明名称 SEMICONDUCTOR MEMORY APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus in which erroneous sensing caused by offset of a sense amplifier can be prevented when operation of a N channel preferential sensing system is performed using a low array voltage. SOLUTION: In this semiconductor memory apparatus, a VBB generating circuit 12 generates back bias voltage VBB to be applied to a pair of first NMOS transistors of a sense amplifier is constituted of a level detecting circuit 20 including a series circuit consisting of a NMOS transistor TN10 of which the operation property is almost the same as the first NMOS transistor, a resistor R1, and a resistor R2, and a comparator 30, a ring oscillator 21, and a charge pump 22, and feedback control is performed so that when Vtn is raised in accordance with threshold value voltage Vtn of the NMOS transistor TN10, an absolute value of the VBB is decreased, when the Vtn is lowered, the absolute value of the VBB is increased. Under such control, sensing operation according to the N channel preferential sensing system is performed. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007073143(A) 申请公布日期 2007.03.22
申请号 JP20050259910 申请日期 2005.09.07
申请人 ELPIDA MEMORY INC 发明人 TSUKADA SHUICHI
分类号 G11C11/408;G11C11/409 主分类号 G11C11/408
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