发明名称 DATA PROCESSING CIRCUIT FOR REDUCING POWER CONSUMPTION BY USING CLOCK CONTROL
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a circuit which operates while reducing power consumption in accordance with throughput of blocks by individually supplying clocks of optimal frequencies to function circuits as needed. <P>SOLUTION: A data processor includes, for example, a reception buffer 101 or 102, a circuit 200 for detecting an effective data amount within the reception buffer, and clock supply circuits 201 and 206 for supplying clocks of different frequencies to circuit blocks in accordance with the amount detected by the detection circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007074607(A) 申请公布日期 2007.03.22
申请号 JP20050261565 申请日期 2005.09.09
申请人 ALAXALA NETWORKS CORP 发明人 MORISHIMA YOSHIYUKI
分类号 H04L12/70;H04L7/00;H04L12/931;H04L13/08 主分类号 H04L12/70
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