| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption and to minimize the performance loss caused by a refresh operation in the semiconductor device which has the mixture of a dynamic random access memory(DRAM) and a logic. SOLUTION: The device is provided with a hierarchy bit line structure and the structure having a first sense amplifier 26 and a main amplifier 7. During normal reading and writing operations, only one word line of a memory cell array block 5 and the first sense amplifier are selected and activated by a word line decoder 6a and a sense amplifier decoder 6b. During a refresh operation, plural memory cell array blocks 5, that are required to be refreshed, are selected and activated simultaneously in order to reduce the power consumption. Moreover, a minimum refresh cycle is easily set by varying the maximum value of an address counter in accordance with the capacity. |
