| 摘要 |
<p>A multi-threaded processor (103) that is capable of responding to, and processing, multiple low-latency-tolerant events concurrently and while using relatively slow, low-power memories (105) is disclosed. The illustrative embodiment comprises a multi-threaded processor, which itself comprises a context controller (301) and a plurality of hardware contexts (302). Each hardware context is capable of storing the current state of one thread in a form that enables the processor to quickly switch to or from the execution of that thread. To enable the processor to be capable of responding to low-latency-tolerant events quickly, each thread - and, therefore, each hardware context is prioritized - depending on the latency tolerance of the thread responding to the event.</p> |
