| 摘要 |
<p>A data reproduction circuit for receiving data and reproducing the data and its clock which comprises an over-sampling determination circuit(31) for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit (33) for adjusting its phase, based on the output of the phase error detection circuit(34), a phase adjustment circuit(35) for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit(32) for supplying the over-sampling determination circuit(31) and the data selection circuit(33) with the newly reproduced clock.</p> |
