发明名称 Method for line etch roughness (LER) reduction for low-k interconnect damascene trench etching
摘要 The present invention provides a method for etching a substrate 100 . The method includes conducting a first etch on an anti-reflective layer 170 and a portion of a hardmask layer 140, 150 to form an opening 162 in the substrate 100 . The first etch is designed to be selective to a remaining portion of the hardmask layer 140, 150 . A second etch, which is different from the first etch, is conducted on a remaining portion of the hardmask 140, 150 , and it is designed to be less selective than the first etch to the remaining portion of the hardmask 140, 150 . The first etch allows polymer to build up on the sidewalls of the opening 162 , and the polymer substantially remains on the sidewalls during the second etch.
申请公布号 US7192880(B2) 申请公布日期 2007.03.20
申请号 US20040952188 申请日期 2004.09.28
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 DOSTALIK, JR. WILLIAM W.
分类号 H01L21/302;H01L21/461 主分类号 H01L21/302
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