发明名称 |
Semiconductor storage device, test method therefor, and test circuit therefor |
摘要 |
A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.
|
申请公布号 |
US7193917(B2) |
申请公布日期 |
2007.03.20 |
申请号 |
US20050498398 |
申请日期 |
2005.01.04 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
TAKAHASHI HIROYUKI;INABA HIDEO;UCHIDA SYOUZOU |
分类号 |
G01R31/28;G11C7/00;G01R31/3185;G11C8/18;G11C11/401;G11C11/403;G11C11/406;G11C29/08;G11C29/14 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|