发明名称 Processor and pipeline reconfiguration control method
摘要 A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
申请公布号 US7194610(B2) 申请公布日期 2007.03.20
申请号 US20050063860 申请日期 2005.02.23
申请人 FUJITSU LIMITED 发明人 URIU SHIRO;WAKAYOSHI MITSUHARU;KAWANO TETSUO;FURUKAWA HIROSHI;KASAMA ICHIRO;IMAFUKU KAZUAKI;SUZUKI TOSHIAKI
分类号 G06F13/00 主分类号 G06F13/00
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