发明名称 Multi-value semiconductor memory device and method capable of caching a lower page data upon an incomplete write of an upper page data
摘要 A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value data; a sense amplifier circuit configured to read data of and write data in the memory cell array; and a controller configured to control data read and write of the memory cell array, wherein the controller has such a function as, when an upper page data write sequence ends in failure, the upper page data being one to be written into an area of the memory cell array where lower page data has already been written, to cache the lower page data read out of the memory cell array and held in the sense amplifier circuit.
申请公布号 US7193896(B2) 申请公布日期 2007.03.20
申请号 US20050167301 申请日期 2005.06.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIGA HITOSHI
分类号 G11C29/04;G11C16/06 主分类号 G11C29/04
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