发明名称 Content addressable memory with reduced test time
摘要 A CAM device having internal circuitry to reduce test time through parallel test setup and parallel pass/fail result generation. A plurality of match results is generated in parallel within a plurality of CAM blocks of the CAM device in response to a search instruction, each match result including a block flag signal that indicates whether a match was detected within a corresponding one of the CAM blocks and a block index that indicates a location of an entry within the one of the CAM blocks. The block index and block flag signal of a highest priority one of the match results is output from the CAM device if an operating mode value indicates a first operating mode, and the block flag signals of the plurality of match results is output from the CAM device if the operating mode value indicates a test operating mode.
申请公布号 US7193877(B1) 申请公布日期 2007.03.20
申请号 US20050256066 申请日期 2005.10.21
申请人 NETLOGIC MICROSYSTEMS, INC. 发明人 YELLURU SADASHIVA R.
分类号 G11C15/04;G11C29/00 主分类号 G11C15/04
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