| 摘要 |
A flip flop circuit is provided to improve transfer characteristics of a latch input signal by reducing load on both nodes as centering an inverter. A first inverter(INV1) inverts a signal of a first node and transfers the inverted signal to a second node. A second inverter(INV2) feeds a signal of the second node back to the first node. The second inverter includes a first PMOS transistor(P3) and a first NMOS transistor(N3) inputting the signal of the second node through a gate, a second PMOS transistor(P2) connected to the first PMOS transistor, receiving a first voltage through a gate and having a longer length than the length of the first PMOS transistor, and a second NMOS transistor(N2) connected to the first NMOS transistor, receiving a second voltage as a gate input and having a longer length than the length the first NMOS transistor. |
