Method for fabricating a memory cell

摘要

Silicon nanocrystals are applied as storage layer ( 6 ) and removed using spacer elements ( 11 ) laterally with respect to the gate electrode ( 5 ). By means of an implantation of dopant, source/drain regions ( 2 ) are fabricated in a self-aligned manner with respect to the storage layer ( 6 ). The portions of the storage layer ( 6 ) are interrupted by the gate electrode ( 5 ) and the gate dielectric ( 4 ), so that a central portion of the channel region ( 3 ) is not covered by the storage layer ( 6 ). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.