发明名称 |
Method of forming interconnection lines for semiconductor device |
摘要 |
The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.
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申请公布号 |
US7192864(B2) |
申请公布日期 |
2007.03.20 |
申请号 |
US20050049730 |
申请日期 |
2005.02.04 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE KYOUNG-WOO;SHIN HONG-JAE;KIM JAE-HAK;WEE YOUNG-JIN;LEE SEUNG-JIN;PARK KI-KWAN |
分类号 |
H01L21/3205;H01L21/4763;H01L21/02;H01L21/311;H01L21/768 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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