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发明名称
半导体装置及其制造方法
摘要
本发明系提供一种可提高具有快闪记忆体之半导体装置之可靠性的技术。于半导体基板1上形成复数个积层图案,该复数个积层图案系自下层依次积层有绝缘膜4、用以形成浮动闸极电极5a之导体膜及绝缘膜,于复数个积层图案之侧面形成侧壁8,并藉由乾蚀刻去除复数个积层图案之相邻间的半导体基板1之损害层后,于复数个积层图案之相邻间之半导体基板1上形成绝缘膜9a,于复数个积层图案之相邻间之绝缘膜9a上,以自我对准复数个积层图案之方式形成复数个辅助闸极电极10a。
申请公布号
TW200711106
申请公布日期
2007.03.16
申请号
TW095102475
申请日期
2006.01.23
申请人
瑞萨科技股份有限公司
发明人
细田直宏;足立哲生
分类号
H01L27/10(2006.01)
主分类号
H01L27/10(2006.01)
代理机构
代理人
陈长文
主权项
地址
日本
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