| 摘要 |
The proposed logic pulse former contains two triggers and two AND-NOT logic elements. The first input of the first logic element is used as the input of the proposed pulse former. The first input of the second logic element is connected to the output of the first logic element, and the output is used as the output of the proposed pulse former. The second input of the second logic element is connected to the inverse output of the first trigger. The second input of the first logic element is connected to the inverse output of the second trigger. The set inputs of the triggers, the direct input of the first trigger, and the inverse input of the second trigger are connected to the output of the proposed pulse former. The reset input of the first trigger is connected to the inverse output of the second trigger. The reset input of the second trigger is connected to the inverse output of the first trigger. The present invention allows the circuit of the pulse former to be simplified.
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