| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout design method of semiconductor integrated circuit, capable of minimizing power consumption of a chip. SOLUTION: In supply voltage drop assumption step S1, it is assumed prior to layout design that maximum supply voltage drop is uniformly distributed to the whole layout area. In arrangement and wiring step S2, cell arrangement and cell-to-cell wiring are performed according to a library having a performance corresponding to the maximum supply voltage drop in a library group 10. In supply voltage drop distribution calculation step S3, supply voltage drop distribution in the layout area is calculated after cell arrangement and cell-to-cell wiring. In layout area division step S4, the layout area is divided by supply voltage drops according to the supply voltage drop distribution. In library substitution step S5, the library used in each divided area is substituted by a library having a performance corresponding to the supply voltage drop of each area in the library group 10. COPYRIGHT: (C)2007,JPO&INPIT
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