发明名称 Semiconductor memory device having memory cells requiring no refresh operation
摘要 A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.
申请公布号 US2007058418(A1) 申请公布日期 2007.03.15
申请号 US20060594800 申请日期 2006.11.09
申请人 RENESAS TECHNOLOGY CORP. 发明人 KIHARA YUJI
分类号 G11C11/24;H01L27/10;H01L21/8244;H01L27/108;H01L27/11;H01L27/12 主分类号 G11C11/24
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