| 摘要 |
A multiple valued SRAM is provided to enhance the degree of integration in the SRAM itself by reducing the number of transistors compared to that of transistors of a conventional multiple valued SRAM. A multiple valued SRAM comprises at least one word line, at least one bit line, a first transistor(N1) composed of a first source connected with a voltage source and a gate and a drain connected with the bit line, and a unit cell(500) at a crossing point between the word line and the bit line. The unit cell includes a second transistor(N2) composed of a second gate connected with the word line and a second drain connected with the bit line, an SET(Single Electron Transistor) element(N4) composed of a fourth gate connected with the second drain and a fourth source connected with a ground voltage, a third transistor(N3) composed of a third gate connected to the ground voltage between the second transistor and the SET element, and a cell capacitor between the second transistor and the ground voltage.
|
