| 摘要 |
The forward error correction based clock and data recovery system according to the invention comprises a data latch ( 16 ) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit ( 20, 21 ) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator ( 23, 24, 25 ) for generating the sampling clock (sclk) depending on the correction signal (ctrl).
|
