发明名称 |
Floating point normalization and denormalization |
摘要 |
A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.
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申请公布号 |
US2007061391(A1) |
申请公布日期 |
2007.03.15 |
申请号 |
US20050226040 |
申请日期 |
2005.09.14 |
申请人 |
TAN DIMITRI;NGUYEN TRINH H |
发明人 |
TAN DIMITRI;NGUYEN TRINH H. |
分类号 |
G06F7/38 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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地址 |
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