发明名称 ASYNCHRONOUS RIPPLE PIPELINE
摘要 An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a single signal, output on the combined acknowledgement and request output (20) of a stage (30), that functions both as a request to the next stage (32) and an acknowledgement to the previous stage (34).
申请公布号 WO2007029168(A2) 申请公布日期 2007.03.15
申请号 WO2006IB53101 申请日期 2006.09.04
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;WIELAGE, PAUL 发明人 WIELAGE, PAUL
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