| 摘要 |
The present invention relates to a alignment measurement system (100, 101) for measuring alignment between a plurality of chips of a device under test (21), the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor (1, 10), comprising
- a multiple capacitors structure (2) integrated in said capacitive sensor (1, 10)
- at least a sensing circuit (8, 8a) connected to said multiple capacitors structure (2) which issues an output voltage (Vout), proportional to a variation of a capacitive value of the multiple capacitors structure (2) of the integrated capacitive sensor (1, 10) of the device under test (21) and corresponding to a measured misalignment between the chips of the device under test (21). |
