| 摘要 |
<p>A clock-signal generation device which changes an average frequency of a clock signal independently of a reference clock signal. A reference-clock-signal generation circuit generates a reference clock signal. A frequency-division circuit divides the frequency of the reference clock signal by using a natural number equal to or greater than one so as to generate a frequency-divided signal. A control circuit controls the frequency-division circuit so as to modify the frequency-divided signal by inserting extension cycles into the frequency-divided signal at predetermined intervals, and output the modified, frequency-divided signal as a clock signal. An output circuit outputs the clock signal generated by the control circuit. Therefore, the average frequency of the clock signal can be set arbitrarily and independently of the reference clock signal.</p> |
