| 摘要 |
A semiconductor memory device is provided to generate data transmission control signals to write data in memory banks of a memory array and to read data from the memory banks by using a column selection signal and a write signal. In a semiconductor memory device receiving data transmission control signals through plural pins of a memory chips from an external test apparatus in order to perform a required operation of a memory array, a column signal generation part(50) generates corresponding bank column signals by receiving one column signal inputted through one pin from the external test apparatus. A write enable signal generation part(60) generates corresponding bank write signals by receiving one write signal inputted from the external test apparatus through another pin. The column signal generation part comprises plural delay parts generating the corresponding bank signals having respective delay time, and a delay amount control part controlling the delay time of each delay part in response to mode registration set data.
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