An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.
申请公布号
WO2006014558(A9)
申请公布日期
2007.03.08
申请号
WO2005US24137
申请日期
2005.07.06
申请人
KENET, INC.;ANTHONY, MICHAEL, P.;KUSHNER, LAWRENCE, J.