| 摘要 |
A chain of processing element ( 10 a , 10, 10 b) with a logic circuit ( 14 ) and a storage element ( 12 ) is provided. The storage elements ( 12 ) of all except a final processing element ( 10 b) in the chain have one or more outputs coupled to the logic circuit ( 14 ) of a next processing element ( 10 a , 10, 10 b) in the chain. A timing circuit ( 16 ) controls respective loading time points at which the storage elements ( 12 ) load data from the logic circuits ( 14 ) in respective ones of the processing elements ( 10 a , 10, 10 b). The data is loaded progressively later in processing elements ( 10 a , 10, 10 b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element ( 10 b) includes loading time points of loading all processing elements ( 10 a , 10 ) other than the final processing element ( 10 ).
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