| 摘要 |
A semiconductor integrated circuit device includes a cell well (CELL P-WELL), a memory cell array (3) formed on the cell well and having a memory cell area (11) and cell well contact area (13), first wiring bodies (BL) arranged in the memory cell area, and second wiring bodies (CPWELL) arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area. ® KIPO & WIPO 2007
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