| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce power consumption and a circuit size while suppressing increase of a logic processing circuit to be added for skew adjustment for parallel signal transmission in a circuit in which high speed performance is requested. <P>SOLUTION: The circuit is constructed by being provided with: a deskew signal creation circuit 12 which creates a deskew signal from a plurality of continuing bits of a data signal by a predetermined logic operation, and transmits to a receiving circuit 2; a skew detection circuit 26 which detects the skew by taking correlation of the deskew signal and the data signal in the receiving circuit 2, and obtaining the average value; and a delay amount adjustment circuit 25 which adjusts the skew by controlling a delay amount of the data signal according to the average value obtained by the skew detection circuit 26. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
