| 摘要 |
PROBLEM TO BE SOLVED: To provide a method wherein a problem generated upon thinning of a wafer is avoided and a process can be shortened for electric connection between laminated wafers. SOLUTION: A deep isolation groove 5a extending from the principal surface of a substrate 1SA (source address) to a requested depth is formed and, thereafter, an insulating film 5b is buried into the deep isolation groove 5a to form a penetrated isolation part 5. Subsequently, an MOS-FET 6 (metal oxide silicon-field effect transistor) is formed on the principal surface of the substrate 1SA, and an interlayer dielectric 8a is deposited on the principal surface of the substrate 1SA. A deep conduction groove 9a is formed as extending from the upper surface of the interlayer dielectric 8a to a depth of halfway of thickness of the substrate 1SA in a region surrounded by the penetrated isolation part 5. Subsequently, the conductor film 9b is buried into the deep conductor groove 9a to form a penetrated wiring unit 9. Thereafter, the backside of the substrate 1SA is ground and polished to a degree that the penetrated separation unit 5 and the penetrated wiring unit 9 will not be exposed, and wet etching process is applied to a degree that a part of lower sections is exposed in the penetrated isolation part 5 and the penetrated wiring unit 9. COPYRIGHT: (C)2007,JPO&INPIT |
