发明名称 CIRCUIT ARRANGEMENT
摘要 PROBLEM TO BE SOLVED: To provide a circuit arrangement which enables suppression of reliability deterioration at the temperature rise by controlling misregistration and film peeling by thermal expansion. SOLUTION: In the circuit arrangement 50, a metal board 1, having a plurality of openings 2 arranged in a circuit substrate 10 interior by a honeycomb arrangement as a core member, is formed. At the end of the top view side of this opening 2, it has a projection 1a, and it has corners (settling) 1b roundish wore on the edge by the side of the lower surface of the opening 2. Interconnect line pattern layers 4 and 6 are formed in both surface sides of this metal board 1 via insulating layers 3 and 5, respectively. Moreover, in order to connect each interconnect line, a conductor layer 8 which connects pattern layer 4 and interconnect line pattern layer 6 via opening 2 is formed by penetrating the metal board 1, and a conduction with each interconnect line pattern layer is obtained. Furthermore, an LSI chip 20 is connected to the top view side of the substrate 10 through a solder ball 21. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007059874(A) 申请公布日期 2007.03.08
申请号 JP20060142272 申请日期 2006.05.23
申请人 SANYO ELECTRIC CO LTD 发明人 SHIBATA SEIJI;USUI RYOSUKE;INOUE YASUNORI
分类号 H05K1/05 主分类号 H05K1/05
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