| 摘要 |
A system clock signal generator circuit comprising a first PLL circuit that is frequency and phase locked to a wobble signal; a frequency and phase comparator for comprising a first output signal from the first PLL circuit with a system clock signal as frequency divided by M and for outputting a second output signal based on the differences in frequency and in phase; a PLL filter for providing a predetermined cutoff to the second output signal to output a third output signal; a pulse width modulating circuit for generating a pulse wave, the carrier frequency of which is a second reference clock signal, and for outputting a fourth output signal obtained by modulating the pulse width of the pulse wave by the third output signal; a low pass filter for smoothing the fourth output signal to output a fifth output signal; a VCO circuit the control voltage of which is the fifth output signal; a first frequency divider circuit for frequency dividing an output signal of the VCO circuit by N to output a system clock signal; and a second frequency divider circuit for frequency dividing, by M, and feeding the system clock signal back to the frequency and phase comparator. ® KIPO & WIPO 2007
|
