CLOCK AND DATA RECOVERY CIRCUIT

摘要

A clock and data recovery circuit is provided to suppress a jitter component of the clock signal for sampling data through an up/down counter and an up/down control circuit by comparing the phase variation of the clock signal with a phase variation of a clock signal for detecting an edge. In a clock and data recovery circuit, a circuit unit has up/down counters(15-17) of which up/down control is performed based on a result of phase comparison. A phase control of a clock signal for detecting an edge is performed by a phase control signal according to a count value of the up/down counters(15-17). A phase control of a clock signal for sampling data is a variable control by stages. The phase control of the clock signal for sampling data progresses or delays a phase without just following the count value of the up/down counter(15-17) when a combination of the current count value of the up/down counter(15-17) and the result of phase comparison satisfies a predetermined condition.