| 摘要 |
PROBLEM TO BE SOLVED: To suppress increase of test cost of a high-speed serial transfer test. SOLUTION: This device is equipped in each channel with a serial-parallel conversion circuit, a frame synchronization circuit, a skew correction circuit, a parallel-serial conversion circuit, a selector and an output buffer. The device is also equipped commonly in a plurality of channels with a synchronization pattern generator for generating parallel data including a frame for synchronization adjustment, a start delimiter, a frame for synchronization confirmation and an end delimiter; an interruption pattern generator for generating an interruption enable signal and an interruption frame; a pattern monitor for outputting a detection flag to the interruption pattern generator when detecting the start delimiter from the parallel data subjected to frame synchronization; and a pattern monitor for comparing a pattern wherein through data and interruption data are merged with an expected value pattern. A test is performed by arranging two chips A, B oppositely. COPYRIGHT: (C)2007,JPO&INPIT
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