| 摘要 |
A vertical nano-wire transistor is formed on a substrate out of a vertical pillar having active regions of opposing conductivity in opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A surround gate is formed around the pillar. The transistor operates by electron tunneling from the source valence band to the gate biasing induced n-type channels along the sidewalls of the pillar to the drain region, thus resulting in a drain current.
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