发明名称 Wafer level chip size package for CMOS image sensor module and manufacturing method thereof
摘要 Disclosed is a wafer level chip size package for an image sensor module and a manufacturing method thereof, more particularly to a small size image sensor module characterized by a structure where a glass formed with an I/R cut-off filter (layer) is assembled onto an image sensor chip by a polymer partition wall and a solder bump is formed on an electrode of the rear side of a chip connected by a through-hole formed on each I/O electrode of an image sensor chip and a wafer level chip size package process for realizing the module. The method for manufacturing a wafer level chip size package for an image sensor module, the method comprises: bonding an image sensor wafer glass and a glass wafer to form a through-hole on the image sensor wafer; filling the through-hole formed on the image sensor wafer with an exciting material; and forming a solder bump at the end of the exciting material to be connected with the circuit formed PCB substrate. According to the present invention, the existing equipments for wafer processing and metal deposition are used. Therefore, it is possible to realize a cost-effective wafer level chip size package and an image sensor module having the minimum thickness in a thickness direction than the existing wafer level chip size package for image sensor and the same area as an image sensor chip.
申请公布号 US2007054419(A1) 申请公布日期 2007.03.08
申请号 US20060513203 申请日期 2006.08.31
申请人 发明人 PAIK KYUNG-WOOK;YIM MYUNG-JIN;SON HO-YOUNG
分类号 H01L21/00;H01L23/02;H01L27/14;H01L27/146;H04N5/335 主分类号 H01L21/00
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