| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can reduce a coupling capacity between layers in a layered bit line structure of a semiconductor memory and coupling capacity noise between adjoining conductors, and which increases reading speed and improves a reading margin. <P>SOLUTION: In the semiconductor storage device provided with a memory circuit for detecting and amplifying a potential difference between global bit line pair GBL/GBLB prepared corresponding to a base unit block column 10 consisting of two or more base unit blocks 1 by a differential type sense amplifier 11, each base unit block 1 is connected to a pair of local bit line LBL, LBLB in common to two or more memory cells 2; the pair of LBL/LBLB is connected to a bit line pre-charge element 3; and includes a transfer gate switching element 4 for controlling the connection between the pair of LBL/LBLB and the pair of GBL/GBLB. The pair of LBL/LBLB and the pair of GBL/GBLB have a layered bit line structure in which the pair of GBL/GBLB is formed in a conductor layer on an upper layer of the pair of LBL/LBLB, and are laid out in parallel, and the pair of GBL/GBLB crosses each other once or more. <P>COPYRIGHT: (C)2007,JPO&INPIT |
