发明名称 SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE
摘要 Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.
申请公布号 IL179080(D0) 申请公布日期 2007.03.08
申请号 IL20060179080 申请日期 2006.11.06
申请人 SIDENSE CORP. 发明人
分类号 G11C11/40;G11C11/401;G11C17/16;H01L;H01L21/28;H01L21/331;H01L21/336;H01L23/525;H01L27/10;H01L27/115;H01L29/423;H01L29/66;H01L29/78 主分类号 G11C11/40
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