| 摘要 |
<p>A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access, wherein an input/output port (211) of a processing module (21), memory interfaces (I/F 222, 232), and memory banks (221-1 to 221-4, 231-1 to 231-4) are connected by connection interconnects arranged in a matrix in a first direction (Y) and a second direction (X) above an arrangement region of a plurality of memory macros (221, 231).</p> |
