| 摘要 |
A DLL(Delay Locked Loop) with an automatic reset function is provided to prevent a fail of a locking operation, by being reset automatically if delay time of a delay circuit part set during a prior locking operation is the maximum or the minimum, when a frequency of an external clock signal is changed. A phase detector(120) detects a phase difference between an input clock signal and first and second reference clock signals, and outputs detection signals according to the detection result. A first delay circuit part(130) is reset in response to a main reset signal or a first sub reset signal, and controls a first delay time in response to the first and second detection signals, and outputs a first delay clock signal by delaying the input clock signal for the controlled first delay time. A second delay circuit part(140) is reset in response to the main reset signal or a second sub reset signal, and controls a second delay time in response to third and fourth detection signals, and outputs a second delay clock signal by delaying the input clock signal for the controlled second delay time. A reset control part(150) generates one or a part of the main reset signal, the first sub reset signal and the second sub reset signal, in response to first and second left flag signals, first and second right flag signals, an external reset signal and a disable signal. The first delay circuit part generates the first left flag signal when the first delay time has a maximum value, and generates the first right flag signal when the first delay time has a minimum value. The second delay circuit part generates the second left flag signal when the second delay time has a maximum value, and generates the second right flag signal when the second delay time has a minimum value. |
