发明名称 Bus arbitration in low power system
摘要 Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.
申请公布号 US7188262(B2) 申请公布日期 2007.03.06
申请号 US20030376816 申请日期 2003.02.28
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 ARENDS JOHN H.;MOYER WILLIAM C.;SCHWARTZ STEVEN L.
分类号 G06F1/00;G06F1/04;G06F1/32;G06F13/36;G06F13/364 主分类号 G06F1/00
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