Phase selectable divider circuit

摘要

A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.