| 摘要 |
A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.
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