发明名称 Digital duty cycle corrector
摘要 A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.
申请公布号 US7187221(B2) 申请公布日期 2007.03.06
申请号 US20040881598 申请日期 2004.06.30
申请人 INFINEON TECHNOLOGIES AG 发明人 KIM JOONHO;KIM JUNG PILL;MINZONI ALESSANDRO
分类号 H03K3/017;H03L7/06 主分类号 H03K3/017
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