发明名称 Multiple network protocol encoder/decoder and data processor
摘要 A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine reacts accordingly to the pertinent data, and any data that are required by more than one data state machine is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location with a pointer designating such data (thereby ensuring minimal memory usage). Resulting display data are immediately passed to a display controller. Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.
申请公布号 USRE39501(E1) 申请公布日期 2007.03.06
申请号 US20020093340 申请日期 2002.03.06
申请人 NVIDIA CORPORATION 发明人 MINAMI JOHN SHIGETO;KOYAMA RYO;JOHNSON MICHAEL WARD;SHINOHARA MASARU;POFF THOMAS C.;BURKES DANIEL F.
分类号 G06F13/00;G06F15/16;H04L12/28;H04L12/56;H04L29/06;H04L29/08 主分类号 G06F13/00
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