SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR SELF-TESTING THEREOF

摘要

A semiconductor memory device and a self test method thereof are provided to reduce test time in order to perform test and recovery operation at the same time, by promptly performing a repair operation whenever a fail is detected in a cell array during a BIST(Built-In Self Test) operation in a chip. A BIST(Built-In Self Test) circuit(21) detects a defective cell while scanning a cell array in response to a test start command from test equipment. A recovery control circuit(30) updates and stores an address corresponding to a tested cell in response to a clock signal, and generates a recovery control signal to fuse a redundancy circuit(23) with the stored address when the defective cell is detected. According to the recovery control circuit, a register(32) generates a recovery master signal to the redundancy circuit, and updates and stores the address corresponding to the tested cell and outputs the stored address. A recovery enable signal generation part generates a recovery enable signal and a recovery disable signal according to the detection number of defective cells. A fuse cut signal generation part outputs a fuse cut signal by latching the defective cell detection signal in response to the clock signal.