| 摘要 |
A semiconductor memory device having a circuit for a wafer burn-in test mode and a wafer burn-in test method are provided to prevent the decrease of sensing stress among bit lines in a dummy cell block while executing a wafer burn-in test as a sense amplifier is not connected to the dummy bit lines biased at power voltage, bit line precharge voltage, or ground voltage. A semiconductor memory device having a circuit for a wafer burn-in test mode is composed of dummy cell blocks(DA1,DA2) having plural memory cells and plural dummy cells; plural normal memory cell blocks(A0~Ak) provided with plural memory cells and arranged between the dummy cell blocks; sense amplifier blocks(B0~Bk+1) disposed between the adjacent normal memory cell blocks and between the normal memory cell block and the dummy cell block; and a test sense amplifier(100) connected to dummy bit lines(BL0~BLn) which are formed in the dummy cell blocks and not connected with sense amplifiers(10,SA) of the sense amplifier blocks, to make test conditions of the dummy cell blocks similar to that of the normal memory cell blocks. |
