发明名称 ERASE ALGORITHM FOR MULTI-LEVEL BIT FLASH MEMORY
摘要 Methods (400) of erasing a sector of multi-level flash memory cells (MLB) having three or more data states (100, 200) to a single data state (1000) are provided. The present invention employs an interactive sector erase algorithm (400) that repeatedly erases (410, 440), verifies (416), soft programs (420, 450), and programs (430) the sector in two or more erase phases to achieve highly compact data state distributions (300, 1000). In one example, the algorithm (400) essentially erases all the MLB cells of the sector to an intermediate state (410, 600) and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase (440, 450), the algorithm further erases all the ML13 cells of the sector using additional interactive erasing (440) and soft programming pulses (450) until a final data state is achieved corresponding to a desired final threshold voltage value (1000) of the cells. Optionally, the algorithm (400) may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state (1000) in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user. ® KIPO & WIPO 2007
申请公布号 KR20070024707(A) 申请公布日期 2007.03.02
申请号 KR20077000365 申请日期 2005.02.11
申请人 SPANSION LLC 发明人 HSIA EDWARD;HAMILTON DARLENE;BATHUL FATIMA;HORIIKE MASATO
分类号 G11C16/34;G11C11/56;G11C16/02;G11C16/10 主分类号 G11C16/34
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